The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2011

Filed:

Jul. 29, 2009
Applicants:

Victor Chiu-kit Fong, San Jose, CA (US);

Eric Bruce Blecker, San Jose, CA (US);

Tom W. Kwan, Cupertino, CA (US);

Ning LI, Fremont, CA (US);

Sumant Ranganathan, Sunnyvale, CA (US);

Chao Tang, Mountain View, CA (US);

Pieter Vorenkamp, Laguna Niguel, CA (US);

Inventors:

Victor Chiu-Kit Fong, San Jose, CA (US);

Eric Bruce Blecker, San Jose, CA (US);

Tom W. Kwan, Cupertino, CA (US);

Ning Li, Fremont, CA (US);

Sumant Ranganathan, Sunnyvale, CA (US);

Chao Tang, Mountain View, CA (US);

Pieter Vorenkamp, Laguna Niguel, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/228 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.


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