The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2011

Filed:

Jul. 10, 2008
Applicants:

Jae-man Yoon, Gyeonggi-do, KR;

Yong-chul OH, Gyeonggi-do, KR;

Hui-jung Kim, Seoul, KR;

Hyun-woo Chung, Seoul, KR;

Kang-uk Kim, Seoul, KR;

Dong-gun Park, Seoul, KR;

Woun-suck Yang, Gyeonggi-do, KR;

Inventors:

Jae-man Yoon, Gyeonggi-do, KR;

Yong-chul Oh, Gyeonggi-do, KR;

Hui-jung Kim, Seoul, KR;

Hyun-woo Chung, Seoul, KR;

Kang-uk Kim, Seoul, KR;

Dong-gun Park, Seoul, KR;

Woun-suck Yang, Gyeonggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/119 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit semiconductor device includes a first transistor formed at a lower substrate and configured with at least one of a vertical transistor and a planar transistor. A bonding insulation layer is formed on the first transistor, and an upper substrate is bonded on the bonding insulation layer. A second transistor configured with at least one of a vertical transistor and a planar transistor is formed at the upper substrate. The first transistor and the second transistor are connected by an interconnection layer.


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