The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Mar. 31, 2008
Huilong Zhu, Poughkeepsie, NY (US);
Hong Lin, Mount Kisco, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Kai Xiu, Pleasantville, NY (US);
Haizhou Yin, Poughkeepsie, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Hong Lin, Mount Kisco, NY (US);
Katherine L. Saenger, Ossining, NY (US);
Kai Xiu, Pleasantville, NY (US);
Haizhou Yin, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure, such as a CMOS semiconductor structure, includes a field effect device that includes a plurality of source and drain regions that are asymmetric. Such a source region and drain region asymmetry is induced by fabricating the semiconductor structure using a semiconductor substrate that includes a horizontal plateau region contiguous with and adjoining a sloped incline region. Within the context of a CMOS semiconductor structure, such a semiconductor substrate allows for fabrication of a pFET and an nFET upon different crystallographic orientation semiconductor regions, while one of the pFET and the nFET (i.e., typically the pFET) has asymmetric source and drain regions.