The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Nov. 26, 2008
Yoshifumi Nishi, Kanagawa, JP;
Yoshinori Tsuchiya, Kanagawa, JP;
Takashi Yamauchi, Kanagawa, JP;
Junji Koga, Kanagawa, JP;
Yoshifumi Nishi, Kanagawa, JP;
Yoshinori Tsuchiya, Kanagawa, JP;
Takashi Yamauchi, Kanagawa, JP;
Junji Koga, Kanagawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.