The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2011

Filed:

May. 08, 2008
Applicants:

Seung-jin Yang, Seoul, KR;

Jeong-uk Han, Suwon-si, KR;

Yong-tae Kim, Yongin-si, KR;

Yong-suk Choi, Hwaseong-si, KR;

Hyok-ki Kwon, Suwon-si, KR;

Inventors:

Seung-Jin Yang, Seoul, KR;

Jeong-Uk Han, Suwon-si, KR;

Yong-Tae Kim, Yongin-si, KR;

Yong-Suk Choi, Hwaseong-si, KR;

Hyok-Ki Kwon, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.


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