The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2011
Filed:
Jul. 21, 2008
Jee-soo Mok, Yongin-si, KR;
Chang-sup Ryu, Yongin-si, KR;
Eung-suek Lee, Ansan-si, KR;
Youn-soo Seo, Suwon-si, KR;
Hee-bum Shin, Gunpo-si, KR;
Yoong OH, Suwon-si, KR;
Byung-bae Seo, Eumseong-gun, KR;
Tae-kyoung Kim, Anyang-si, KR;
Dong-jin Park, Suwon-si, KR;
Jee-Soo Mok, Yongin-si, KR;
Chang-Sup Ryu, Yongin-si, KR;
Eung-Suek Lee, Ansan-si, KR;
Youn-Soo Seo, Suwon-si, KR;
Hee-Bum Shin, Gunpo-si, KR;
Yoong Oh, Suwon-si, KR;
Byung-Bae Seo, Eumseong-gun, KR;
Tae-Kyoung Kim, Anyang-si, KR;
Dong-Jin Park, Suwon-si, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon, KR;
Abstract
A printed circuit board using paste bumps and manufacturing method thereof are disclosed. The method of manufacturing a printed circuit board using paste bumps, includes: (a) perforating a core board to form at least one via hole, (b) filling the at least one via hole by fill-plating and forming a circuit pattern on at least one surface of the core board, (c) stacking a paste bump board on at least one surface of the core board, and (d) forming an outer layer circuit on a surface of the paste bump board, a structurally stable all-layer IVH structure can be implemented due to increased strength in the BVH's of the plated core boards, the manufacture time can be reduced due to parallel processes and collective stacking, implementing micro circuits can be made easy due to the copper foils of the paste bump boards stacked on the outermost layers, the manufacture costs can be reduced as certain plating and drilling processes may be omitted, the interlayer connection area is increased between circuit patterns for improved connection reliability, and dimple coverage can be obtained.