The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7970591 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 28, 2011

Filed:

Jul. 08, 2008
Applicant:

Curtis L. Ratzlaff, Austin, TX (US);

Inventor:

Curtis L. Ratzlaff, Austin, TX (US);

Assignee:

Nascentric, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, a method for simulating an electric circuit that is represented as one or more partitions, each partition comprising a plurality of constituents representing portions of the circuit, wherein at least one of the constituents is a variable constituent for which the corresponding portion of the electronic circuit includes non-linear behavior, comprises: determining a first matrix for the variable constituent, wherein the first matrix describes a system of equations that represents a behavior of the variable constituent; determining a second matrix for the partition, wherein the second matrix permits calculation of short circuit currents from open circuit voltages according to a node tearing analysis method; and simulating a timestep of the simulation, the simulating comprising iteratively solving a state of the partition using successive guesses of the state of the variable constituent, wherein each iteration comprises solving the variable constituent independently to generate the open circuit voltages using the first matrix, applying the second matrix to determine the short circuit currents, and resolving the variable constituent with the short circuit currents applied and the forcing functions disabled; converging to a solution during the iteratively solving; and solving the partition state for the timestep responsive to the convergence.


Find Patent Forward Citations

Ratzlaff, Curtis. (2011). Using impedance (z) parameters to augment circuit simulation (U.S. Patent No. 7970591). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7970591

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…