The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 28, 2011
Filed:
Nov. 27, 2007
Tatsuo Sasaoka, Osaka, JP;
Yasuhiro Sugaya, Osaka, JP;
Eiji Kawamoto, Osaka, JP;
Kazuhiko Honjo, Osaka, JP;
Toshiyuki Asahi, Osaka, JP;
Chie Sasaki, Osaka, JP;
Hiroaki Suzuki, Hyogo, JP;
Tatsuo Sasaoka, Osaka, JP;
Yasuhiro Sugaya, Osaka, JP;
Eiji Kawamoto, Osaka, JP;
Kazuhiko Honjo, Osaka, JP;
Toshiyuki Asahi, Osaka, JP;
Chie Sasaki, Osaka, JP;
Hiroaki Suzuki, Hyogo, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A passive component incorporating interposer includes a double-sided circuit board () having a wiring layer () on both sides, a passive component () mounted on the wiring layer () on one surface of the double-sided circuit board (), a second insulating layer () made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board () mounted with the passive component (), a first insulating layer () made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board () not mounted with the passive component (), first and second wiring layers () formed on the first and second insulating layers (), and a through hole () for electrically connecting the wiring layers () disposed on both surfaces of the double-sided circuit board () and the first and second wiring layers (), where the first wiring layer () is formed to enable mounting of a semiconductor element ().