The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2011
Filed:
Jul. 31, 2008
Eric A. Foreman, Fairfax, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
David J. Hathaway, Underhill, VT (US);
Jerry D. Hayes, Milton, VT (US);
Anthony D. Polson, Jericho, VT (US);
Eric A. Foreman, Fairfax, VT (US);
Peter A. Habitz, Hinesburg, VT (US);
David J. Hathaway, Underhill, VT (US);
Jerry D. Hayes, Milton, VT (US);
Anthony D. Polson, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.