Semiconductor devices including fine pitch arrays with staggered contacts

Abstract

A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the contacts. The contacts of one row communicate with every other active-device region and are staggered relative to the contacts of another row, which communicate with the remaining active-device regions. Each contact may include a relatively large contact plug with a relatively large upper surface to provide a relatively large amount of tolerance as a contact hole for an upper portion of the contact that is formed. The contact holes may be formed substantially simultaneously with trenches for conductive traces, such as bit lines, in a dual damascene process. Intermediate structures are also disclosed, as are methods for designing semiconductor device structures.