The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2011

Filed:

Feb. 12, 2008
Applicants:

Kerry Bernstein, Underhill, VT (US);

Timothy Joseph Dalton, Ridgefield, CT (US);

Jeffrey Peter Gambino, Westford, VT (US);

Mark David Jaffe, Shelburne, VT (US);

Paul David Kartschoke, Williston, VT (US);

Anthony Kendall Stamper, Williston, VT (US);

Inventors:

Kerry Bernstein, Underhill, VT (US);

Timothy Joseph Dalton, Ridgefield, CT (US);

Jeffrey Peter Gambino, Westford, VT (US);

Mark David Jaffe, Shelburne, VT (US);

Paul David Kartschoke, Williston, VT (US);

Anthony Kendall Stamper, Williston, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.


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