Method for manufacturing a mosfet with a surrounding gate of bulk si

Abstract

A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiOoxide layer/SiN dielectric layer on the bulk Si; electron beam exposure; etching two adjacent slots; depositing SiN sidewalls; isotropically etching Si; dry oxidation; removing SiN by wet etching; forming the nanowire by stress self-constraint oxidation; depositing and anisotropically etching oxide dielectric layer and planarizing surface; releasing the nanowire by wet etching while keeping sufficiently thick SiOat bottom as isolation; growing gate dielectric and depositing gate material; etching back the gate and isotropically etching the gate material by using the gate dielectric as a block layer; shallow implantation in the source/drain region; depositing and etching sidewalls; deep implantation in the source/drain region to form contact. The present invention eliminates self-heating effect and floating-body effect, and is easy to integrate. The present invention is also advantageous in suppression of short channel effect and enables the size of the MOSFET to be smaller.