The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Sep. 28, 2007
Applicant:
Neyaz Khan, Plano, TX (US);
Inventor:
Neyaz Khan, Plano, TX (US);
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data.