Serial bit ordering of non-synchronous bus signals

Abstract

The quantity of input and output signal lines that must be directly supported by a bus logic to transmit signals to and receive signals from bus devices is minimized by serializing the states to be driven onto the output signal lines and serially transmitting those states to one or more external shift registers having parallel outputs to drive output signal lines, by receiving states of input signal lines at parallel inputs to one or more other external shift registers to be serialized and serially transmitted to the bus logic, wherein the order in which the states to be driven onto the output signal lines is such that those states corresponding to actual output signal lines are the last states to be serially transmitted, and wherein the order in which the states received from the input signal lines are transmitted to the bus logic is such that those states corresponding to actual input signal lines are transmitted first to the bus logic, thereby also minimizing the quantity of shift registers required externally of the bus logic.