The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2011
Filed:
Jan. 28, 2008
Toshiyuki Enda, Zushi, JP;
Hirosyoshi Tanimoto, Yokohama, JP;
Takashi Izumida, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nonvolatile semiconductor memory device relating to one embodiment of this invention includes a substrate, a plurality of memory strings formed on said substrate, said memory string having a first select gate transistor, a plurality of memory cells and a second select gate transistor, said first select gate transistor having a first pillar semiconductor, a first gate insulation layer formed around said first pillar semiconductor and a first gate electrode being formed around said first gate insulation layer; said memory cell having a second pillar semiconductor, a first insulation layer formed around said second pillar semiconductor, a storage layer formed around said first insulation layer, a second insulation layer formed around said storage layer and first to nth electrodes (n is a natural number 2 or more) being formed around said second insulation layer, said first to nth electrodes being spread in two dimensions respectively, said second select gate transistor having a third pillar semiconductor, a second gate insulation layer formed around said third pillar semiconductor and a second gate electrode being formed around said second gate insulation layer, and a channel region of at least either said first select gate transistor or said second select gate transistor formed by an opposite conductive type semiconductor to a source region and a drain region.