The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2011

Filed:

Jul. 30, 2010
Applicants:

Yuhao Luo, San Jose, CA (US);

Shuxian Wu, San Jose, CA (US);

Xin X. Wu, Fremont, CA (US);

Jae-gyung Ahn, Pleasanton, CA (US);

Deepak K. Nayak, Fremont, CA (US);

Daniel Gitlin, Palo Alto, CA (US);

Inventors:

Yuhao Luo, San Jose, CA (US);

Shuxian Wu, San Jose, CA (US);

Xin X. Wu, Fremont, CA (US);

Jae-Gyung Ahn, Pleasanton, CA (US);

Deepak K. Nayak, Fremont, CA (US);

Daniel Gitlin, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
Abstract

A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.


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