The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2011

Filed:

Oct. 20, 2009
Applicants:

Yifeng Wu, Goleta, CA (US);

Marcia Moore, Santa Barbara, CA (US);

Tim Wisleder, Auckland, NZ;

Primit Parikh, Goleta, CA (US);

Inventors:

Yifeng Wu, Goleta, CA (US);

Marcia Moore, Santa Barbara, CA (US);

Tim Wisleder, Auckland, NZ;

Primit Parikh, Goleta, CA (US);

Assignee:

Cree, Inc., Goleta, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 21/338 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device, and particularly a high electron mobility transistor (HEMT), having a plurality of epitaxial layers and experiencing an operating (E) field. A negative ion region in the epitaxial layers to counter the operating (E) field. One method for fabricating a semiconductor device comprises providing a substrate and growing epitaxial layers on the substrate. Negative ions are introduced into the epitaxial layers to form a negative ion region to counter operating electric (E) fields in the semiconductor device. Contacts can be deposited on the epitaxial layers, either before or after formation of the negative ion region.


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