The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 31, 2011

Filed:

Jun. 29, 2007
Applicants:

Qi Wang, San Jose, CA (US);

Pinhong Chen, Saratoga, CA (US);

Mitchell W. Hines, San Jose, CA (US);

Inventors:

Qi Wang, San Jose, CA (US);

Pinhong Chen, Saratoga, CA (US);

Mitchell W. Hines, San Jose, CA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.


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