The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Sep. 30, 2008
Qi Xiang, San Jose, CA (US);
Albert Ratnakumar, San Jose, CA (US);
Jeffrey Xiaoqi Tung, Milpitas, CA (US);
Weiqi Ding, Fremont, CA (US);
Qi Xiang, San Jose, CA (US);
Albert Ratnakumar, San Jose, CA (US);
Jeffrey Xiaoqi Tung, Milpitas, CA (US);
Weiqi Ding, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.