The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2011
Filed:
Feb. 02, 2009
Applicants:
Atsuo Takatori, Kawasaki, JP;
Shuji Hamada, Kawasaki, JP;
Inventors:
Atsuo Takatori, Kawasaki, JP;
Shuji Hamada, Kawasaki, JP;
Assignee:
Fujitsu Semiconductor Limited, Yokohama, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
A logic circuit includes a gated clock buffer including a control node, being set in either a first state or a second state in response to an input signal applied to the control node, outputting an input clock signal supplied as an output signal in the first state, and fixing an output signal to a constant value in the second state, a plurality of scan flip-flops receiving the output signal of the gated clock buffer, and included in at least part of a scan chain, and a combinational logic circuit coupled to at least one of the plurality of scan flip-flops.