The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 24, 2011

Filed:

Feb. 26, 2008
Applicants:

Dae-gyu Park, Poughquaq, NY (US);

Michael P Chudzik, Danbury, CT (US);

Rashmi Jha, Beacon, NY (US);

Siddarth a Krishnan, Peekskill, NY (US);

Naim Moumen, Walden, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi Paruchuri, New York, NY (US);

Inventors:

Dae-Gyu Park, Poughquaq, NY (US);

Michael P Chudzik, Danbury, CT (US);

Rashmi Jha, Beacon, NY (US);

Siddarth A Krishnan, Peekskill, NY (US);

Naim Moumen, Walden, NY (US);

Vijay Narayanan, New York, NY (US);

Vamsi Paruchuri, New York, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a 'p' interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the 'p' interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed.


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