The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2011

Filed:

Jun. 18, 2009
Applicants:

Satoshi Kameda, Saitama, JP;

Masaru Doi, Saitama, JP;

Shinya Sato, Saitama, JP;

Inventors:

Satoshi Kameda, Saitama, JP;

Masaru Doi, Saitama, JP;

Shinya Sato, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a test apparatus having a bad block memory for storing a plurality of pieces of fail information in association with blocks of a memory under test, each piece of fail information indicating whether there is a defect in the associated block. The test apparatus writes a test data sequence to a page under test of the memory under test, reads the test data sequence written to the page under test, and compares the read data sequence to the written data sequence. The test apparatus includes an allocation register that stores allocation information for setting which of the plurality of fail conditions for judging whether there is a defect in the page under test are allocated to the plurality of pieces of fail information. The test apparatus detects whether there is a defect corresponding to each of a plurality of fail conditions, outputs the detection result as a fail signal, and updates a plurality of pieces of fail information associated with the block including the page under test using the fail signal corresponding to the allocated fail conditions.


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