The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2011

Filed:

Feb. 12, 2008
Applicants:

Katsuhiko Yoshihara, Matsumoto, JP;

Rikihiro Maruyama, Matsumoto, JP;

Masaaki Chino, Nagano, JP;

Eiji Mochizuki, Matsumoto, JP;

Motokiyo Yokoyama, Azumino, JP;

Tatsuo Nishizawa, Tokyo, JP;

Tomonobu Sugiyama, Tokyo, JP;

Inventors:

Katsuhiko Yoshihara, Matsumoto, JP;

Rikihiro Maruyama, Matsumoto, JP;

Masaaki Chino, Nagano, JP;

Eiji Mochizuki, Matsumoto, JP;

Motokiyo Yokoyama, Azumino, JP;

Tatsuo Nishizawa, Tokyo, JP;

Tomonobu Sugiyama, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes an outer resin case having a peripheral wall and terminal mounting holes formed in the peripheral wall, and a layer assembly provided in the outer resin case. The layer assembly includes a semiconductor chip, an insulating circuit board on which the semiconductor chip is mounted, and a heat-dissipating metal base. External terminals having leg portions are arranged in mounting holes of the peripheral wall, and are press-fitted into the terminal-mounting holes. Bonding wires connect the terminal leg portions and a conductive pattern of the insulating circuit board or the semiconductor chip.


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