The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 17, 2011
Filed:
Jan. 27, 2009
Oliver Haeberlen, Villach, AT;
Walter Rieger, Arnoldstein, AT;
Lutz Goergens, Villach, AT;
Martin Poelzl, Ossiach, AT;
Johannes Schoiswohl, Villach, AT;
Joachim Krumrey, Goedersdorf, AT;
Oliver Haeberlen, Villach, AT;
Walter Rieger, Arnoldstein, AT;
Lutz Goergens, Villach, AT;
Martin Poelzl, Ossiach, AT;
Johannes Schoiswohl, Villach, AT;
Joachim Krumrey, Goedersdorf, AT;
Infineon Technologies Austria AG, Villach, AT;
Abstract
One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.