The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 17, 2011

Filed:

Jan. 13, 2009
Applicants:

Joseph Paul Ellul, San Jose, CA (US);

Khanh Tran, Milpitas, CA (US);

Albert Bergemont, Palo Alto, CA (US);

Inventors:

Joseph Paul Ellul, San Jose, CA (US);

Khanh Tran, Milpitas, CA (US);

Albert Bergemont, Palo Alto, CA (US);

Assignee:

Maxim Integrated Products, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.


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