The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2011
Filed:
Apr. 25, 2005
Ken Wadland, Grafton, MA (US);
Richard Allen Woodward, Jr., San Diego, CA (US);
Randall Lawson, Westford, MA (US);
Walter Katz, Boulder, CO (US);
Wiley Gillmor, Boulder, CO (US);
Ken Wadland, Grafton, MA (US);
Richard Allen Woodward, Jr., San Diego, CA (US);
Randall Lawson, Westford, MA (US);
Walter Katz, Boulder, CO (US);
Wiley Gillmor, Boulder, CO (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method and system that converges on a global solution to a PCB routing problem using iterations of topology-based routing is described. In some embodiments, the geometric design space is abstracted into a topological graph representing the routing problem. Then, each net is allowed to find its optimal solution path independent of the solution paths for all other nets. The electrical and physical constraints of the system are initially ignored or greatly relaxed. Over each design iteration, the constraints are tightened until a complete, global, topological solution is found. Once a topological solution is found, it is converted into a geometric solution. In the event that no geometric solution exists for that topological solution, then the iteration process is resumed taking into consideration this additional information. The result is the ability to quickly autoroute highly-constrained PCB designs with minimal operator input.