The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2011
Filed:
Sep. 25, 2008
James M. Little, Sacramento, CA (US);
Perry Leigh Heedley, Folsom, CA (US);
David Vieira, San Jose, CA (US);
Maoyou Sun, Folsom, CA (US);
James M. Little, Sacramento, CA (US);
Perry Leigh Heedley, Folsom, CA (US);
David Vieira, San Jose, CA (US);
Maoyou Sun, Folsom, CA (US);
Vintomie Networks B.V., LLC, Dover, DE (US);
Abstract
A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below −80 dBc.