The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2011
Filed:
Nov. 25, 2008
Chandrasekaram Ramiah, Phoenix, AZ (US);
Douglas G. Mitchell, Tempe, AZ (US);
Michael F. Petras, Phoenix, AZ (US);
Paul W. Sanders, Scottsdale, AZ (US);
Chandrasekaram Ramiah, Phoenix, AZ (US);
Douglas G. Mitchell, Tempe, AZ (US);
Michael F. Petras, Phoenix, AZ (US);
Paul W. Sanders, Scottsdale, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming () desired device regions () with contacts () on the front surface () of an initially relatively thick wafer ('); etching () via cavities () partly through the wafer (′) in the desired locations; filling () the via cavities () with a conductive material () coupled to some device region contacts (); mounting () the wafer (′) with its front side () facing a support structure (); thinning () the wafer (′) from the back side () to expose internal ends (, etc.) of the conductive material filled vias (, etc.); applying () any desired back-side interconnect region () coupled to the exposed ends (, etc.) of the filled vias; removing () the support structure () and separating the individual device or IC assemblies () so as to be available for mounting () on a further circuit board, tape or larger circuit ().