The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2011

Filed:

Oct. 18, 2004
Applicants:

Frederick R. Gruner, Palo Alto, CA (US);

Gaurav Singh, Santa Clara, CA (US);

Elango Ganesan, Palo Alto, CA (US);

Samir C. Vora, Milpitas, CA (US);

Christopher M. Eccles, San Francisco, CA (US);

Brian Hang Wai Yang, Monterey Park, CA (US);

Inventors:

Frederick R. Gruner, Palo Alto, CA (US);

Gaurav Singh, Santa Clara, CA (US);

Elango Ganesan, Palo Alto, CA (US);

Samir C. Vora, Milpitas, CA (US);

Christopher M. Eccles, San Francisco, CA (US);

Brian Hang Wai Yang, Monterey Park, CA (US);

Assignee:

NetLogic Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2006.01); H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.


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