The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2011

Filed:

Nov. 05, 2007
Applicants:

Sally Foong, Milpitas, CA (US);

Kevin Guan, Richmond, CA (US);

Changhak Lee, Cupertino, CA (US);

Lai Nguk Chin, Penang, MY;

Royce Yeoh Kao Tziat, Penang, MY;

Foong Yue Ho, Penang, MY;

Inventors:

Sally Foong, Milpitas, CA (US);

Kevin Guan, Richmond, CA (US);

Changhak Lee, Cupertino, CA (US);

Lai Nguk Chin, Penang, MY;

Royce Yeoh Kao Tziat, Penang, MY;

Foong Yue Ho, Penang, MY;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/02 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.


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