The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
Dec. 26, 2007
Oleg Levitsky, San Jose, CA (US);
Kit Lam Cheong, Palo Alto, CA (US);
Wilson Chan, San Mateo, CA (US);
Dongzi Liu, Cupertino, CA (US);
Oleg Levitsky, San Jose, CA (US);
Kit Lam Cheong, Palo Alto, CA (US);
Wilson Chan, San Mateo, CA (US);
Dongzi Liu, Cupertino, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.