The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2011
Filed:
Sep. 24, 2008
Mark A. Lavin, Katonah, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
Mark A. Lavin, Katonah, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Louise H. Trevillyan, Katonah, NY (US);
Hua Xiang, Ossining, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention provides a method, system and program product for mitigating effects of interconnect variability during a design stage of a chip. Under the technique of the present invention, a global and detailed routing of interconnects of the chip are determined. Thereafter, a dummy fill estimation and a grid based metal density estimation are performed. Then, based on a CMP model, a variable map of metal thicknesses is obtained. Based on the variable map, wiring nets of the chip that are sensitive to metal variability (e.g., that fail to meet timing closure due to metal thickness loss/gain in the CMP process) are identified. These wiring nets are then re-routed for optimization of the chip.