The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 12, 2011

Filed:

Sep. 30, 2003
Applicants:

Philippe Diehl, Versailles, FR;

Marc Vieillot, Montigny le Bretonneux, FR;

Cyril Quennesson, Antony, FR;

Gilles Laurent, Boulogne, FR;

Frederic Reblewski, Paris, FR;

Inventors:

Philippe Diehl, Versailles, FR;

Marc Vieillot, Montigny le Bretonneux, FR;

Cyril Quennesson, Antony, FR;

Gilles Laurent, Boulogne, FR;

Frederic Reblewski, Paris, FR;

Assignee:

Mentor Graphics Corporation, Wilsonville, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/56 (2006.01); H01L 25/00 (2006.01); G06F 9/455 (2006.01); G06F 3/00 (2006.01); G06F 11/22 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.


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