The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2011
Filed:
Oct. 02, 2009
Masao Nakayama, Ritto, JP;
Tsunehiro Takagi, Nagaokakyo, JP;
Masahiko Inamori, Ibaraki, JP;
Kaname Motoyoshi, Nishinomiya, JP;
Masao Nakayama, Ritto, JP;
Tsunehiro Takagi, Nagaokakyo, JP;
Masahiko Inamori, Ibaraki, JP;
Kaname Motoyoshi, Nishinomiya, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.