The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2011
Filed:
May. 09, 2008
Balvinder Singh, Haryana, IN;
Donald O'riordan, Sunnyvale, CA (US);
Bogdan George Arsintescu, San Jose, CA (US);
Alka Goel, Haryana, IN;
Devendra Ramakant Deshpande, Noida, IN;
Balvinder Singh, Haryana, IN;
Donald O'Riordan, Sunnyvale, CA (US);
Bogdan George Arsintescu, San Jose, CA (US);
Alka Goel, Haryana, IN;
Devendra Ramakant Deshpande, Noida, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.