The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2011

Filed:

Oct. 24, 2006
Applicants:

Sergei Drizlikh, Scarborough, ME (US);

Ashish Kushwaha, South Portland, ME (US);

Thomas James Moutinho, Gorham, ME (US);

David Tucker, Falmouth, ME (US);

Inventors:

Sergei Drizlikh, Scarborough, ME (US);

Ashish Kushwaha, South Portland, ME (US);

Thomas James Moutinho, Gorham, ME (US);

David Tucker, Falmouth, ME (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.


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