The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7911861 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 22, 2011

Filed:

Oct. 29, 2008
Applicants:

Toru Ishikawa, Chuo-ku, JP;

Shotaro Kobayashi, Chuo-ku, JP;

Inventors:

Toru Ishikawa, Chuo-ku, JP;

Shotaro Kobayashi, Chuo-ku, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device may include a memory that stores data, an input/output unit and a loopback circuit. The input/output unit inputs and outputs data of a predetermined number of bits in synchronization with a clock signal. The input/output unit may include, but is not limited to, the same number of data input/output terminals as the predetermined number of bits. The loopback circuit performs loopback operation to read data of the predetermined number of bits out of a first optional area of the memory and to write the data into a second optional area of the memory.


Find Patent Forward Citations

Ishikawa, Toru. (2011). Semiconductor memory device and method of testing semiconductor memory device (U.S. Patent No. 7911861). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7911861

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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