The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Dec. 18, 2008
Dai Nakamura, Kawasaki, JP;
Hiroyuki Kutsukake, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Takeshi Shimane, Matsudo, JP;
Mitsuhiro Noguchi, Yokohama, JP;
Koji Hosono, Fujisawa, JP;
Masaru Koyanagi, Tokyo, JP;
Takashi Aoi, Yokohama, JP;
Dai Nakamura, Kawasaki, JP;
Hiroyuki Kutsukake, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Takeshi Shimane, Matsudo, JP;
Mitsuhiro Noguchi, Yokohama, JP;
Koji Hosono, Fujisawa, JP;
Masaru Koyanagi, Tokyo, JP;
Takashi Aoi, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.