The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
Feb. 27, 2008
Rouying Zhan, Gilbert, AZ (US);
Chai Ean E. Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Hongzhong Xu, Gilbert, AZ (US);
Rouying Zhan, Gilbert, AZ (US);
Chai Ean E. Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Hongzhong Xu, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An electrostatic discharge (ESD) protection device () coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (″), each stage (″) comprising first (T, T', T″, etc.) and second transistors (T, T′, T′″ etc.) having a common collector (″) and first (″) and second (″) emitters providing terminals (″) of each clamp stage (. A first emitter () of the first stage () couples to the common terminal () and a second emitter (″) of the last stage (′) couples to the I/O terminals (). Zener diode triggers are not used. Integrated external ESD trigger resistors (″) (e.g., of poly SC) are coupled between the base (″) and emitter (″) of each transistor (T, T′, T″; T, T′, T″). Different resistor values (e.g., ˜0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages () gives even higher trigger voltages. The ESD trigger resistances (″) are desirably located outside the common collector-isolation wall (″) surrounding the transistors (T, T′, T″; T, T′, T″).