The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 22, 2011
Filed:
May. 30, 2008
Sang-jin Hyun, Gyeonggi-do, KR;
Si-young Choi, Gyeonggi-do, KR;
In-sang Jeom, Seoul, KR;
Gab-jin Nam, Seoul, KR;
Sang-bom Kang, Seoul, KR;
Sug-hun Hong, Gyeonggi-do, KR;
Sang-jin Hyun, Gyeonggi-do, KR;
Si-young Choi, Gyeonggi-do, KR;
In-sang Jeom, Seoul, KR;
Gab-jin Nam, Seoul, KR;
Sang-bom Kang, Seoul, KR;
Sug-hun Hong, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.