The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 15, 2011
Filed:
Feb. 24, 2009
Frederick A. Ware, Los Altos Hills, CA (US);
Lawrence Lai, San Jose, CA (US);
Chad A. Bellows, Burlingame, CA (US);
Wayne S. Richardson, Saratoga, CA (US);
Frederick A. Ware, Los Altos Hills, CA (US);
Lawrence Lai, San Jose, CA (US);
Chad A. Bellows, Burlingame, CA (US);
Wayne S. Richardson, Saratoga, CA (US);
RAMBUS Inc., Sunnyvale, CA (US);
Abstract
A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.