The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2011

Filed:

Apr. 24, 2009
Applicants:

Hideo Nomura, Tokyo, JP;

Tomonori Hayashi, Tokyo, JP;

Yuji Sugiyama, Tokyo, JP;

Inventors:

Hideo Nomura, Tokyo, JP;

Tomonori Hayashi, Tokyo, JP;

Yuji Sugiyama, Tokyo, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.


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