The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Jul. 31, 2007
Shashidhar Anil Thakur, Santa Clara, CA (US);
Rahul Hari Dani, San Jose, CA (US);
Ramnath N. Rao, Milpitas, CA (US);
Shashidhar Anil Thakur, Santa Clara, CA (US);
Rahul Hari Dani, San Jose, CA (US);
Ramnath N. Rao, Milpitas, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constraints, on random values for signals to be input to the circuit during simulation of the design. Application of the rules identifies one or more templates of goal(s) to be met. The computer is programmed to automatically use constraint(s) and template(s) to instantiate goal(s) in memory. Each goal identifies a signal to be input to the circuit, and defines a counter for a value of the signal. The goals are used in the normal manner, i.e. used to measure coverage of functional verification during simulation of the design of the circuit.