The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Jul. 28, 2003
Suresh Marisetty, San Jose, CA (US);
Mani Ayyar, Cupertino, CA (US);
Nhon T. Quach, San Jose, CA (US);
Bernard J. Lint, Mountain View, CA (US);
Suresh Marisetty, San Jose, CA (US);
Mani Ayyar, Cupertino, CA (US);
Nhon T. Quach, San Jose, CA (US);
Bernard J. Lint, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.