The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2011

Filed:

Jun. 07, 2007
Applicants:

Anthony Babella, Salida, CA (US);

Allan Wong, Folsom, CA (US);

Lance Cheney, Davis, CA (US);

Brian D. Rauchfuss, Shingle Springs, CA (US);

Inventors:

Anthony Babella, Salida, CA (US);

Allan Wong, Folsom, CA (US);

Lance Cheney, Davis, CA (US);

Brian D. Rauchfuss, Shingle Springs, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to return test instructions from the cache to the execution units in response to a request from one execution unit for the test instructions from the cache in the design test mode. The execution units execute the test instructions during the design test mode. Interrupts are prevented during the design test mode.


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