The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
Dec. 09, 2008
Pankaj Kumar, Karnataka, IN;
Makeshwar Kothandaraman, Whitehall, PA (US);
Dipankar Bhattacharya, Macungie, PA (US);
John Kriz, Palmerton, PA (US);
Jeffrey J. Nagy, Allentown, PA (US);
Pramod Elamannu Parameswaran, Bangalore, IN;
Pankaj Kumar, Karnataka, IN;
Makeshwar Kothandaraman, Whitehall, PA (US);
Dipankar Bhattacharya, Macungie, PA (US);
John Kriz, Palmerton, PA (US);
Jeffrey J. Nagy, Allentown, PA (US);
Pramod Elamannu Parameswaran, Bangalore, IN;
LSI Corporation, Milpitas, CA (US);
Abstract
Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.