The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 08, 2011
Filed:
May. 31, 2007
Alberto O. Adan, Ikoma, JP;
Mitsuhiro Kikuta, Kyotanabe, JP;
Akinobu Teramoto, Sendai, JP;
Tadahiro Ohmi, Sendai, JP;
Hiroo Yabe, Susono, JP;
Takanori Watanabe, Susono, JP;
Alberto O. Adan, Ikoma, JP;
Mitsuhiro Kikuta, Kyotanabe, JP;
Akinobu Teramoto, Sendai, JP;
Tadahiro Ohmi, Sendai, JP;
Hiroo Yabe, Susono, JP;
Takanori Watanabe, Susono, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
National University Corporation Tohoku University, Miyagi, JP;
Yazaki Corporation, Tokyo, JP;
Abstract
In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than −8° and not more than +8° off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than −8° and not more than +8° off the silicon crystal direction.