The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2011

Filed:

Sep. 20, 2007
Applicants:

Sang Jine Park, Gyeonggi-do, KR;

Richard O. Henry, Hopewell Junction, NY (US);

Yong Siang Tan, Hopewell Junction, NY (US);

O Sung Kwon, Wappingers Falls, NY (US);

OH Jung Kwon, Hopewell Junction, NY (US);

Inventors:

Sang Jine Park, Gyeonggi-do, KR;

Richard O. Henry, Hopewell Junction, NY (US);

Yong Siang Tan, Hopewell Junction, NY (US);

O Sung Kwon, Wappingers Falls, NY (US);

Oh Jung Kwon, Hopewell Junction, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, sacrificial nitride spacers on opposing sidewalls of the gate electrode and source/drain regions, which are self-aligned to the sacrificial nitride spacers, on a semiconductor substrate. The sacrificial nitride spacers are selectively removed using a diluted hydrofluoric acid solution having a nitride-to-oxide etching selectivity in excess of one. In order to increase charge carrier mobility within a channel of the field effect transistor, a stress-inducing electrically insulating layer is formed on opposing sidewalls of the gate electrode. This insulating layer is configured to induce a net tensile stress (NMOS) or compressive stress (PMOS) in the channel.


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