The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2011
Filed:
Apr. 10, 2008
Charles J. Alpert, Cedar Park, TX (US);
Zhuo LI, Cedar Park, TX (US);
Tuhin Mahmud, Austin, TX (US);
Stephen T. Quay, Austin, TX (US);
Paul G. Villarrubla, Austin, TX (US);
Charles J. Alpert, Cedar Park, TX (US);
Zhuo Li, Cedar Park, TX (US);
Tuhin Mahmud, Austin, TX (US);
Stephen T. Quay, Austin, TX (US);
Paul G. Villarrubla, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for concurrent buffering and layer assignment in integrated current layout. Buffers are inserted and metal interconnects or 'wires' are sized for every net, which consists of one driver and one or more receivers, such that timing skew constraints can be met. Long nets are promoted to a higher level if the slew violation can be fixed only by a promotion of the net or if the 'slack' gain available by this promotion is equal to or greater than a predesignated layer of promotion threshold. In response to determining these layer assignments, the method and system then systematically demotes nets that are not critical and which do not impact the circuit and electrical constraints in order to minimize the use of high layer wire resources.