The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2011

Filed:

Jun. 25, 2009
Applicants:

Gregory E Howard, Dallas, TX (US);

Vikas Gupta, Dallas, TX (US);

Darvin R Edwards, Garland, TX (US);

Inventors:

Gregory E Howard, Dallas, TX (US);

Vikas Gupta, Dallas, TX (US);

Darvin R Edwards, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

One embodiment of the invention is a semiconductor system () of arrays (, etc.) of packaged devices. Each array includes a sheet-like substrate (, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (, etc.), which adheres to the substrate, embeds the connected components. Metal posts (, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.


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